Process Step and Analysis of Bit Cost for Stacked Type MRAM with NOR Structured Cell

In this paper the process step and analysis of bit cost of stacked type MRAM with NOR structured cell has been newly described. For NOR structure 4 layer process is needed for realizing 1 layer memory cell compared with 2 layer for NAND structure. Estimated bit cost for stacked type NOR MRAM is very small, 0.04-0.4, compared with that of 1 layered NAND flash memory. This shows that not only NAND structure but also NOR structure is promising candidate for realizing ultra low bit cost non-volatile memory. For the further reduction of bit cost for NOR structure the reduction of process steps/layer and reduction of memory cell area are key issues.